
CHAPTER 9 TARGET SYSTEM INTERFACE CIRCUITS
9.5
FLMD0, FLMD1
74LV125
74LV125
Figure 9-5. FLMD0 and FLMD1 Pins
V DD
33 ?
V DD2
Signal
PG-FP4
Target system
9.6
V DD , V DD2
When V DD and V DD2 are supplied from the target system, the PG-FP4 internal voltage regulator is protected.
Figure 9-6. V DD and V DD2 Pins
V DD /V DD2
generator
Transistor
Polyswitch
350 mA
V DD or V DD2
A/D input
0.01 μ F
2 k ?
1 k ?
1 k ?
0.1 μ F
PG-FP4
Target system
104
User ’s Manual U15260EJ4V0UM